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ltc 4226 1 4226f typical a pplica t ion fea t ures descrip t ion wide operating range dual hot swap controller the lt c ? 4226 dual hot swap? controller allows two power paths to be safely inserted and removed from a live backplane or powered connector. using n-channel pass transistors, supply voltages ranging from 4.5 v to 44v are ramped up at an adjustable rate. three selectable ratios of current limit to circuit breaker threshold accommodate noisy loads and momentary high peak currents without interruption, while a dual-rate fault timer protects the mosfet from extended output over- current events. fault outputs indicate the circuit breaker status. the ltc4226-1 remains off after a fault while the ltc4226-2 automatically retries after a 0.5s delay. the ltc4226 can also be configured as a bidirectional cur- rent limiter/circuit breaker. for high current applications, two channels may be configured as parallel power paths. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 2 port firewire application inrush after load connection a pplica t ions n allows safe board insertion into live backplane n selectable current limit and dual-rate timer accommodate load surges n fast response limits peak fault current n wide operating voltage range: 4.5v to 44v n optional auto-retry or latchoff after over current fault n high side drive for external n-channel mosfet n allows parallel power paths for high current applications n available in 16-pin qfn (3mm 3mm) and msop packages n apple firewire/ieee 1394 n disk drives n rugged 12v, 24v applications n hot board/connector insertion n uni/bidirectional current limiter/circuit breaker smcj33a* *36.7v to 40.6v bv ftmr1 gnd 220nf 7v to 33v current limit select 30m ss3p5 fdms86500dc 30m fdms86500dc 220nf ftmr2 on1 v cc1 sense1 gate1 ltc4226-2 out1 v cc2 sense2 gate2 out2 fault1 cls fault2 on2 port 1 1394 socket 1394 plug 4226 ta01a port 2 1394 socket 1394 plug 4226 ta01b 1ms/div v cc 10v/div v out 10v/div v cc = 12v c load = 1mf i out 1a/div cable insertion inrush current
ltc 4226 2 4226f a bsolu t e maxi m u m r a t ings v ccn ........................................................... C0. 3 v to 55 v sensen , onn , fa u ltn , cls ....................... C 0.3 v to 55 v gaten ( note 3) .......................................... C 0.3 v to 68 v outn ( note 3) ............................................ C 0.3 v to 55 v gaten C outn ( note 3) ............................. C 0.3 v to 18 v ftmrn ......................................................... C 0.3 v to 4v operating ambient temperature range ltc 4226 c ................................................ 0 c to 70 c ltc 4226 i ............................................. C4 0 c to 85 c storage temperature range .................. C 65 c to 150 c msop lead temperature ( soldering , 10 sec ) ........ 30 0 c (notes 1, 2) o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc4226cud-1#pbf ltc4226cud-1#trpbf lfrc 16-lead (3mm 3mm) plastic qfn 0c to 70c ltc4226cud-2#pbf ltc4226cud-2#trpbf lfrd 16-lead (3mm 3mm) plastic qfn 0c to 70c ltc4226iud-1#pbf ltc4226iud-1#trpbf lfrc 16-lead (3mm 3mm) plastic qfn C40c to 85c ltc4226iud-2#pbf ltc4226iud-2#trpbf lfrd 16-lead (3mm 3mm) plastic qfn C40c to 85c ltc4226cms-1#pbf ltc4226cms-1#trpbf 42261 16-lead plastic msop 0c to 70c ltc4226cms-2#pbf ltc4226cms-2#trpbf 42262 16-lead plastic msop 0c to 70c ltc4226ims-1#pbf ltc4226ims-1#trpbf 42261 16-lead plastic msop C40c to 85c ltc4226ims-2#pbf ltc4226ims-2#trpbf 42262 16-lead plastic msop C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 16 15 14 13 5 6 7 8 top view ud package 16-lead (3mm 3mm) plastic qfn 17 9 10 11 12 4 3 2 1v cc1 sense1 gate1 out1 v cc2 sense2 gate2 out2 on1 fault1 fault2 on2 ftmr1 gnd cls ftmr2 t jmax = 125c, ja = 68c/w exposed pad (pin 17), pcb gnd connection optional 1 2 3 4 5 6 7 8 fault1 on1 v cc1 sense1 gate1 out1 ftmr1 gnd 16 15 14 13 12 11 10 9 fault2 on2 v cc2 sense2 gate2 out2 ftmr2 cls top view ms package 16-lead plastic msop t jmax = 125c, ja = 120c/w p in c on f igura t ion
ltc 4226 3 4226f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v cc = 12v. symbol parameter conditions min typ max units supplies v ccn input supply range l 4.5 44 v i ccn input supply current v cc = 12v l 0.7 2 ma v ccn(uvl) input supply undervoltage lockout v cc rising l 3 3.7 4.5 v ?v ccn( hyst) input supply undervoltage lockout hysteresis 200 mv circuit breaker and current limit v cb circuit breaker threshold (v cc C sense) l 45 50 55 mv channel-to-channel v cb mismatch l 6 % v limit current limit voltage (v cc C sense), cls = 0v (v cc C sense), cls = open (v cc C sense), cls = 3v l l l 70 93 139 86 115 173 103 136 205 mv mv mv channel-to-channel v limit mismatch l 6 % i sense sense pin input current (v cc C sense = 0v) l 40 200 a gate drive ?v gate external n-channel gate drive (gate C out) i gate = 0a, C1a; v cc > 6v i gate = 0a, C1a; v cc < 6v l l 10 8 12 12 16 16 v v i gate(up) gate pull-up current gate = out = 1v l C5 C9 C13 a i gate(dn) gate pull-down current gate = 12v, out = 0v, on = 0v gate = out = v cc = 12v, on = 0v or fault = 0v gate = 5v, out = 0v, on = 3v, severe fault l l l 1 50 100 3 150 200 5 300 1000 ma a ma comparator inputs v on on pin threshold voltage v on rising l 1.17 1.24 1.3 v ?v on(hyst) on pin hysteresis voltage 50 mv i on on pin input current v on = 1.2v l 0 1 a fault timer i ftmr(cb) ftmr pin pull-up current (circuit breaker) v ftmr = 0v, circuit breaker fault l C1.4 C2 C2.6 a i ftmr(cl) ftmr pin pull-up current (current limit) v ftmr = 0v, current limit engaged, cls = 0v v ftmr = 0v, current limit engaged, cls = open v ftmr = 0v, current limit engaged, cls = 3v l l l C14 C25 C56 C20 C36 C80 C26 C46 C104 a a a i ftmr(def) ftmr pin pull-down current (default) v ftmr = 1v, default l 1.4 2 2.6 a i ftmr(rst) ftmr pin pull-down current (reset) v ftmr = 1v, reset l 70 100 130 a v ftmr(h) ftmr pin threshold voltage (trip) l 1.17 1.23 1.3 v v ftmr(l) ftmr pin threshold voltage (reset) l 0.1 0.2 v fault i/o v (ol) fault pin low output voltage circuit breaker fault, i fault = 2ma l 0.2 0.4 v i (ol) fault pin low output pull-down current circuit breaker fault, v fault = 5v, v cc = 12v l 2 5 10 ma v fault fault pin input threshold voltage no internal fault, external input l 0.3 0.5 0.8 v i (oh) fault pin pull-up current no internal fault, v fault = 2v l C5 C10 C20 a v (oh) fault pin high output voltage no internal fault, i fault = 0a, v cc = 12v l 2 3.8 5 v
ltc 4226 4 4226f e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive, all voltages are referenced to gnd unless otherwise specified. note 3: limits on maximum rating is defined as whichever limit occurs first. internal clamps limit the gate pin to a minimum of 12 v above out, a diode voltage drop below out, or a diode voltage drop below gnd. driving the gate to out pin voltage beyond the clamp may damage the device. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v cc = 12v. symbol parameter conditions min typ max units three-state input v cls(l) cls pin low threshold voltage l 0.4 v v cls(h) cls pin high threshold voltage l 2 v v cls(z) cls pin voltage in open state 1.38 v i cls(z) allowable cls pin leakage in open state l 2 a i cls(l) cls pin low input current l C2 C4 C8 a i cls(h) cls pin high input current l 2 4 8 a timing delay t off(sense) severe overcurrent fault to gate low c gate = 1nf, (v cc C sense = 4v) l 0.1 1 s t off( fault) fault input low to gate low c gate = 1nf l 3 6 30 s t off(fmtr) ftmr high to gate low c gate = 1nf l 3 7 30 s t off(on) on low to gate low c gate = 1nf l 25 60 s t off(uvlo) v cc enters undervoltage to gate low c gate = 1nf l 25 60 s t on(on) on high to gate high v cc above undervoltage l 5 10 20 ms channel-to-channel t on(on) mismatch l 10 % t on(uvl) v cc exits undervoltage to gate high on high l 25 50 100 ms channel-to-channel t on(uvl) mismatch l 10 % t d(cool) auto-retry delay ltc4226-2 only l 0.25 0.5 1 s
ltc 4226 5 4226f v cc (v) 0 v limit (mv) 200 150 100 50 4226 g04 50 20 40 10 30 cls = open cls = 3v cls = 0v i gate(up) (a) ?15 ?10 ?5 0 4226 g07 temperature (c) ?50 100 50 0 75 ?25 25 ?v gate (v) 15 10 5 0 4226 g08 i gate(up) (a) 0 ?15 ?10 ?5 v cc (v) 0 ?v gate (v) 15 10 5 0 4226 g09 50 20 40 10 30 v limit (mv) 200 150 100 50 4226 g05 cls = open cls = 3v cls = 0v temperature (c) ?50 100 50 0 75 ?25 25 sense voltage (v in ? v sense ) (mv) active current limit delay (s) 4226 g06 100 10 1 0.1 0.01 c gate = 1nf cls = 3v cls = 0v 0 600 400 200 500 100 300 cls = open typical p er f or m ance c harac t eris t ics current limit voltage vs supply voltage gate pull-up current vs temperature current limit voltage vs temperature gate voltage vs gate pull-up current active current limit delay vs sense voltage gate voltage vs supply voltage supply current vs supply voltage circuit breaker voltage vs supply voltage circuit breaker voltage vs temperature t a = 25c, v cc = 12v, unless otherwise noted. v cc (v) 0 i cc (a) 1000 800 600 400 200 0 4226 g01 50 20 40 10 30 v cc (v) 0 v cb (mv) 60 55 50 45 40 4226 g02 50 20 40 10 30 temperature (c) ?50 v cb (mv) 55.0 52.5 50.0 47.5 45.0 4226 g03 100 50 0 75 ?25 25
ltc 4226 6 4226f typical p er f or m ance c harac t eris t ics gate voltage vs gate pull-down current gate voltage vs severe fault gate pull-down current gate voltage vs temperature circuit breaker timer current vs temperature fault input threshold voltage vs temperature current limit timer current vs temperature supply undervoltage lockout vs temperature fault output low voltage vs current on turn-on time vs temperature t a = 25c, v cc = 12v, unless otherwise noted. i gate(dn) (ma) 0 ?v gate (v) 15 10 5 0 4226 g10 5 2 4 1 3 on = 0v temperature (c) ?50 i ftmr(cb) (a) ?2.6 ?2.4 ?2.2 ?2.0 ?1.8 ?1.6 ?1.4 4226 g13 100 50 0 75 ?25 25 temperature (c) ?50 v fault (v) 0.8 0.7 0.6 0.5 0.4 0.3 4226 g16 100 50 0 75 ?25 25 temperature (c) ?50 t on(on) (ms) 15 13 11 9 7 5 4226 g18 100 50 0 75 ?25 25 temperature (c) ?50 v cc(uvl) (v) 4.0 3.8 3.6 3.4 3.2 3.0 4226 g17 100 50 0 75 ?25 25 v cc(uvl) v cc(uvl) ? ?v cc(hyst) temperature (c) ?50 i ftmr(cl) (a) ?110 ?90 ?70 ?50 ?30 ?10 4226 g14 100 50 0 75 ?25 25 cls = open cls = 3v cls = 0v i ol (ma) 0 v ol (v) 5 4 3 2 1 0 4226 g15 10 4 8 2 6 i gate(dn) (ma) 0 ?v gate (v) 15 10 5 0 4226 g11 500 200 400 100 300 ?v gate (v) 15 10 5 0 4226 g12 temperature (c) ?50 100 50 0 75 ?25 25
ltc 4226 7 4226f p in func t ions cls: three-state current limit select input. tying this pin low enables 1.5 current limit; opening this pin enables 2 current limit and tying this pin high ( above 2 v) enables 3 current limit. a higher current limit selection permits larger current transients to pass without invoking current limiting. the cls pin permits dynamic current limit selection. the three input states configure the preset current limit volt- age v limit to approximately 1.5, 2 or 3 of 1.15 ? v cb . exposed pad: the exposed pad may be left open or con- nected to device ground. fau lt1, fau lt2: fault input/output status. when the ftmr pin has reached the v ftmr(h) threshold, the fault status is set active and the fault pin output pulls low. when fault is inactive, a 10 a current source pulls this pin up to a diode below its internal supply voltage. pulling the fault pin low turns off the external mosfet without affecting the ftmr pin status. the fault pin is not latched. ftmr1, ftmr2: fault timer. a capacitor sets the dual- rate fault timer durations: circuit breaker cb timeout and current limit cl timeout. the ftmr pin pulls up with i ftmr(cb) when the sense resistor voltage is between v cb and v limit . the ftmr pin pulls up with i ftmr(cl) when the sense resistor voltage is at or above v limit . ftmr pulls low with i ftmr(def) when the sense resistor volt- age falls below v cb . when the ftmr voltage reaches the v ftmr(h) threshold, the fault status is activated. to reset ftmr, the on pin can be pulled low or the correspond- ing supply voltage can be pulled below the undervoltage lockout threshold. the capacitor on the ftmr pin is pulled to gnd with i ftmr(rst) to clear the fault status. for the ltc4226-1 latchoff option, the mosfet remains off until faults are cleared by cycling the on pin or by an under- voltage condition on the corresponding supply. for the ltc4226-2 auto-retry option, after a t d(cool) delay, ftmr is reset, the fault status is cleared, and the gate begins to ramp up. the ltc4226-2 can be forced to restart by cycling the on pin or by an undervoltage condition on the corresponding supply. gate1, gate2: gate drive for external mosfet. the gate driver controls the external n-channel mosfet switch by applying a voltage across the gate and out pins which connect to the mosfet gate and source pins. a charge pump sources 9 a at the gate pin to turn on the external mosfet. when the mosfet is on, the gate pin voltage is clamped at ?v gate above the out pin. during turn-off, the gate pin is discharged by a 3 ma pull-down with about 2.85 ma of current flowing to the out pin. in a severe fault, the gate pin is discharged to the out pin with a minimum of 100 ma. when the mosfet is off, the gate pin is pulled towards ground with 150 a and a voltage clamps limits the gate voltage to a diode drop below the out pin. gnd: device ground on1, on2: on control inputs. the on pins have a 1.23 v threshold with 50 mv of hysteresis. a high input turns on the external mosfet with a 10 ms delay. a low input turns off the external mosfet and resets circuit breaker faults. out1, out2: gate drive return. connect this pin to the source of the external n-channel mosfet switch. this pin provides a return for the gate pull-down circuit. when the gate pin is below the out pin, the internal clamp diode draws current from this out pin. sense1, sense2: current sense negative input. the circuit breaker comparator and the current limit amplifier monitor the voltage across the sense resistor. the current limiting amplifier controls the gate of the external mosfet to keep the sense resistor voltage at v limit . the current limit is set higher than the circuit breaker to accommodate noisy loads that momentarily exceed the circuit breaker comparator threshold. v cc1 , v cc2 : supply voltage and current sense positive input. an undervoltage lockout circuit disables the mos- fet switch until v cc is above the lockout voltage v cc(uvl) for 50ms.
ltc 4226 8 4226f func t ional b lock diagra m ? + ? + 4226 bd on1 v cc1 v cb v limit sense1 sense2 ftmr1 cls gnd gate1 out1 fault1 v cc2 ? + ? + + ? ? + + ? on v ref ? + ftmr(h) v ref ? + ftmr(l) 0.1v uvlo logic channel 1 charge pump 9a 10a i ftmr(cl) cl cl cb v cb v limit + ? + ? uvlo cl cb i ftmr(rst) rst i ftmr(cb) on2 gate2 out2 ? + on v ref charge pump 9a 12v 12v cb i ftmr(def) def ftmr2 fault2 ? + ftmr(h) v ref ? + ftmr(l) 0.1v logic channel 2 10a i ftmr(cl) cl i ftmr(rst) rst i ftmr(cb) cb i ftmr(def) def
ltc 4226 9 4226f o pera t ion the ltc4226 controls two independent hot swap channels. it is designed to turn each supply voltage on and off in a controlled manner, allowing live insertion into a powered connector or backplane. the ltc4226 powers-up the output of a channel when that channels v cc pin has remained above the 3.7 v undervolt- age lockout threshold v cc(uvl) for more than 50 ms and its on pin has remained above the v on threshold for more than 10 ms. during normal operation, a charge pump turns on the external n-channel mosfet providing power to the load. each channels charge pump derives its power from its own v cc supply pin. to protect the mosfet, the gate voltage is clamped at about 12 v above the out pin. it is also clamped a diode voltage below the out pin and a diode voltage below gnd. the current flowing through the mosfet is measured by the external sense resistor. the sense voltage across the sense resistor is measured between the v cc and sense pins. the ltc4226 has a circuit breaker ( cb) comparator to detect the sense current above circuit breaker thresh- old and a current limit ( cl) amplifier to actively clamp the sense current at the current limit threshold. both the cb comparator and the cl amplifier monitor the sense resistor voltage between the v cc and sense pins. when the sense voltage exceeds v cb but is below v limit , the cb comparator enables a 2 a i ftmr(cb) current source that ramps up the voltage on the ftmr pin. if the sense resistor voltage exceeds v limit , the cl amplifier limits the current in the mosfet by reducing the gate-to-out voltage with an active control loop. the fast response cl amplifier can quickly gain control of the gate-to-out voltage in the event of an out-to-gnd short circuit. the ftmr pin is ramped up by the larger i ftmr(cl) current source during active current limiting. if the sense voltage falls below v cb , the ftmr is ramped down by the default 2a i ftmr(def) pull-down current. a fault timeout occurs when an overcurrent condition persists above v cb that causes the ftmr pin to ramp to the v ftmr(h) threshold. when this occurs, the mosfet is turned off and the fault pin asserts low. the ftmr has two timeout durations: a longer cir cuit breaker (cb) timeout with a lower current i ftmr(cb) ramp up when the current limit is not activated and a shorter current limit (cl) timeout with a higher current i ftmr(cl) ramp up if current limit is active. the cls input state sets the higher current i ftmr(cl) at 20 a when cls = 0 v ; 36 a when cls = open; 80a when cls > 2v. during current limit, the sense voltage is at v limit . there can be significant mosfet power dissipation while in cur- rent limit due to the substantial drain-to-source voltage. the cl timeout duration should be selected based on the external mosfet safe-operating-area to prevent mosfet damage. the cl timeout is set by the ftmr capacitor c t and the i ftmr(cl) pull-up to the v ftmr(h) threshold. setting the current limit higher than the circuit breaker threshold allows momentary current load spikes as long as the average current remains below the circuit breaker limit. both channels share a common current limit select, cls pin. this pin has three input states: low, open and high. the three input states configure the preset current limit v limit to approximately 1.5, 2 or 3 of 1.15 ? v cb . after a fault timeout, the auto-retry ( ltc4266-2) version waits 0.5 seconds before resetting ftmr. after the ftmr capacitor is discharged, the gate pin is free to ramp up again after the fault pin resets high. for the latchoff (ltc4266-1) version, there is no 0.5 second restart delay. for both versions, ftmr can be reset by cycling the on pin low and then high or by cycling v cc below and then above uvlo. the fault pin pulls low when active with a 5 ma current limit. the pin can drive a low-current 2 ma led with a series resistor connected to v cc . the fault pin has an internal 10 a pull-up current to a diode below its internal v cc when signaling no fault. pulling the fault pin below the v fault threshold causes the external mosfet to turn off without affecting ftmr status. the fault pin can be wire-ored with other open-drain outputs. the output voltage of the hot swap circuit is ramped down when the on pin transitions low or v cc falls below the 3.7 v undervoltage lockout. the gate driver discharges the gate pin with 3ma (including 2.85 ma to the out pin ) when gate > out and 150 a to gnd when gate < out.
ltc 4226 10 4226f a pplica t ions i n f or m a t ion the typical ltc4226 application is in high availability systems that distribute positive voltage supplies between 4.5v to 44 v to hot-swappable ports or cards. it can also be used in daisy chain port applications like firewire to provide instant current limit. the basic two channel applications are shown in figure 1 and figure 2. figure 1 shows the ltc4226 in a card resident application with an upstream connector. figure 2 shows the ltc4226 on a backplane or motherboard with a downstream connector. each hot swap channel has a power path con- trolled by an external mosfet switch and a sense resistor for monitoring current. turn-on sequence during turn-on, a 9 a current charges the gate of the mosfet switch: q1 for channel 1. the current limit am- plifier monitors the current in the channel 1 power path by sensing the voltage across the resistor, r s1 . at start-up, the switch current is typically dominated by the current charging the load capacitor, c l1 . if the sense voltage reaches v limit , the current limit amplifier controls the gate of the mosfet in a closed loop. this keeps the start-up inrush current at the current limit. several conditions must be present before the external mosfet can be turned on. the fault timer ftmr is reset by either uvlo or on low status. the external supply v cc must exceed its undervoltage lockout level v cc(uvl) for more than 50 ms. the on pin must be high for more than 10ms and the fault pin must be high before the external mosfet turns on with no additional delay. if the channel is not in uvlo, the on pin low to high asser- tion delay is 10 ms. the fault pin must be high before the external switch turns on. when the channel is not in uvlo and the on pin is high, there is no delay from the fault low to high transition to turn on of the external switch. figure 1. 2-channel card resident controller with upstream connector 5v z2 smcj7v0a r s2 10m q2 fdms86500dc or si7164dp ftmr1 gnd c t1 33nf c l1 100f r1 720k z1 smcj15a r s1 5m q1 fdms86500dc or si7164dp c t2 33nf ftmr2 on1 v cc1 sense1 gate1 ltc4226-1 out1 v cc2 sense2 gate2 out2 fault1 cls fault2 on2 on1 12v fault2 on2 12v 8.9a out 4226 f01 connector 1 connector 2 backplane plug-in card gnd fault1 cls + c l2 220f 5v 4.45a out + r2 100k c1 470pf r3 240k r7 1k r6 1k r4 100k c2 470pf c3 22nf r5 10k
ltc 4226 11 4226f figure 2. 2-channel backplane resident controller with downstream connector r2 240k 5v z2 smcj7v0a r s2 10m q2 fdms86500dc or si7164dp ftmr1 gnd c t1 33nf c l1 100f r1 720k 12v z1 smcj15a r s1 5m q1 fdms86500dc or si7164dp c t2 33nf ftmr2 on1 v cc1 sense1 gate1 ltc4226-1 out1 v cc2 sense2 gate2 out2 fault1 cls fault2 on2 on1 fault1 cls fault2 on2 r2 100k c1 470pf r4 100k c2 470pf 5v 4.45a out 12v 8.9a out gnd connector 2 connector 1 motherboard or backplane plug-in card 4226 f02 + c l2 220f + a pplica t ions i n f or m a t ion figure 3. 2-channel controller with a common on/off connection 5v z2 smcj7v0a r s2 10m q2 fdms86500dc or si7164dp ftmr1 gnd c t1 33nf c l1 100f r1 720k 12v z1 smcj15a r s1 5m q1 fdms86500dc or si7164dp c t2 33nf ftmr2 on1 v cc1 sense1 gate1 ltc4226-1 out1 v cc2 sense2 gate2 out2 fault1 cls fault2 on2 cls fault on2 5v 4.45a out 12v 8.9a out gnd connector 2 connector 1 motherboard plug-in card 4226 f03 + c l2 220f + r2 100k c1 470pf
ltc 4226 12 4226f a pplica t ions i n f or m a t ion figure 4. 2-channel controller with inrush current control but without connector enable 5v z2 smcj7v0a r s2 10m q2 fdms86500dc or si7164dp ftmr1 gnd c t1 33nf c l1 100f 12v z1 smcj15a r s1 5m q1 fdms86500dc or si7164dp c t2 33nf ftmr2 on1 v cc1 sense1 gate1 ltc4226-1 out1 v cc2 sense2 gate2 out2 fault1 cls fault2 on2 cls fault on2 c2 220f c1 100f 5v 4.45a out 12v 8.9a out gnd connector 2 connector 1 motherboard connector plug-in card or connector 4226 f04 + + + c l2 220f + r g1 10 c g1 10nf r g2 10 c g1 10nf turn-off sequence the mosfet switch can be turned off by a variety of con- ditions. a normal turn-off is initiated by the on pin going low. additionally, a circuit breaker/ current limit timeout will cause the mosfet to turn off, as will v cc dropping below its undervoltage lockout potential v cc(uvl) . alternatively, the fault pin can be externally pulled low to force the gate shutdown. under any of these conditions, the mosfet is turned off with a 3 ma current pulling down from gate. about 2.85 ma of that current flows from gate to out and the remainder flows to gnd. when the gate voltage is below the out pin, the gate is pulled towards gnd by a 150a current source. inrush current control in most applications, keeping the inrush current at current limit is an acceptable start- up method if it does not trip the fault timer ftmr and the mosfet has an adequate safe operating margin. to keep the inrush sense resistor voltage below the circuit breaker threshold voltage v cb , a resistor r g and a capacitor c g can be inserted between the gate pin and ground as shown in figure 4. the capacitor c g with a grounded terminal and interconnect inductance can lead to parasitic mosfet oscillations. a resistor r g between 10 and 100 is typically adequate to prevent parasitic oscillation. r g also allows c g to act as a charge reservoir during current limit while preserving the fast pull- down of the gate. the capacitor c g should be sized to limit the inrush current below the circuit breaker trip current. for leaded mosfet with heatsink, an additional 10 resistor ( as shown with r 1 in figure 13) can be added close to the mosfet gate pin to prevent possible parasitic oscillation due to more trace/ wire inductance and capacitance. the mosfet is turned on by a 9 a current source charging up the gate. when the gate voltage reaches the mosfet threshold voltage, the mosfet turns on and the source voltage follows the gate voltage as it increases. the gate voltage rises with a slope 9a/c g and the supply inrush current is: i inrush = c l c g ? 9a 1 ( ) note that the voltage across the mosfet switch can be large during inrush current control. if the inrush current is below the circuit breaker threshold, the fault timer ftmr is not activated. in some applications like firewire where a large supply voltage step up transient can occur, the current limit amplifier is momentarily activated and the gate is partially discharged. once the switch current falls below the current limit, the gate will continue to charge up at the supply inrush control rate.
ltc 4226 13 4226f a pplica t ions i n f or m a t ion overcurrent fault the ltc4226 manages overcurrent faults by differentiat- ing between circuit breaker faults and current limit faults. typical applications have a load capacitor to filter the load current. a large load capacitor is an effective filter, but it can increase mosfet switch power dissipation at start-up or during step up supply transients. when the mosfet is fully enhanced and the current is below the current limit, the mosfet power dissipation is low and is determined by the r dson and the switch cur- rent. if the current is above the circuit breaker threshold but below current limit, the circuit breaker cb comparator activates a i ftmr ( cb ) pull - up current source at the ftmr pin . when the channel current exceeds the current limit, the cl amplifier activates the gate driver pull-down in a closed loop manner. the excess gate overdrive voltage is abruptly discharged to the out pin until the sense voltage between v cc and sense drops below v limit . this brief interval is kept short by the fast responding amplifier to reduce the excessive channel current. next the cl amplifier servos the gate pin to maintain the sense voltage at v limit . during this current limit inter val, the power dissipation in the mosfet increases. the worst case switch power dissipation occurs during a load short where the current is set by the current limit with the entire supply voltage appearing across the mosfet. during active current limit- ing, the ftmr pin is pulled up with i ftmr(cl) . dual-rate fault timer the fault timer pin ftmr, as illustrated in figure 5 timing waveforms, has a dual-rate fault pull-up that extends the allowable duration of peak currents that are above the circuit breaker threshold but below the current limit level. when the load current exceeds the current limit threshold, the power dissipation in the mosfet may be high due to the potentially large drain-to-source voltage. in this condition, the ftmr pull-up current increases to reduce the fault timer duration. when the load current is below the current limit threshold, the power dissipation in the mosfet is less since the mosfet is fully enhanced and the drain-to-source voltage is small. therefore, when the current is below the current limit threshold but above the circuit breaker threshold, the ftmr pull-up current is re- duced. the mosfet will turn off in a fault condition where the average current is above the circuit breaker threshold, but the dual-rate timer extends the allowable duration for peak currents that remain below the current limit level. the ftmr pin has comparators and four current sources connected to an external capacitor c t . the four current sources are: the default pull-down current i ftmr(def) , the circuit breaker pull-up current source i ftmr(cb) , the higher current limit pull-up current source i ftmr(cl) and the reset pull-down current source i ftmr(rst) . when the ftmr pin voltage exceeds the v ftmr(h) threshold, the ftmr comparator signals a fault timeout. the ftmr pin is held low in default normal mode whenever the circuit breaker comparator, the current limit amplifier and the reset are all inactive. the default mode has the i ftmr(def) pull-down current source activated. when the sense voltage exceeds the circuit breaker threshold v cb but is below v limit , the circuit breaker comparator enables the i ftmr ( cb ) pull - up current source and disables the i ftmr ( def ) current source. when the sense voltage reaches the v limit threshold, the current limit amplifier activates the higher i ftmr(cl) pull-up current source. when the ftmr pin ramps up to v ftmr(h) , the ftmr(h) comparator trips. the fault pin is asserted low and the gate to out voltage is discharged to turn off the mosfet. for the auto-retry option, the auto-retry internal timing is initiated. the ftmr pin is asserted high at v ftmr(h) until the ftmr(l) comparator is reset low at v ftmr(l) by the i ftmr(rst) pull-down source, which is activated by on low or uvlo or at the end of the auto-retry interval of typically 0.5 s. the fault pin goes high when the ftmr 4226 f05 ftmr v out i out i cb i lim mosfet off modest overload ignored severe overload shuts off figure 5. dual-rate fault timing
ltc 4226 14 4226f a pplica t ions i n f or m a t ion pin is pulled below v ftmr(l) . the gate to out voltage can ramp up for auto-retry mode if the on pin is high and v cc is not in uvlo. when the mosfet current exceeds the circuit breaker threshold but remains below the current limit the fault time is given by: t cb = c t ? 1.23v i ftmr(cb) 2 ( ) when the current limit is active the fault time is given by: t limit = c t ? 1.23v i ftmr(cl) (3) during active current limiting, a large mosfet drain to source voltage can appear, and t limit should be selected appropriately based on the worst mosfet safe-operating- area with the out pin shorted to ground. a i ftmr(rst) pull-down source is active when resetting the fault status. the current sources at the ftmr pin can be overdriven externally. the ftmr pin can be pulled high externally above v ftmr (h) to force a fault status or the ftmr pin can be pulled low externally towards ground to force a reset status. both the fault and gate pins behave the same way for externally driven ftmr as described above for internal mode. a prolonged external pull-down is not recommended as it may mask normal ftmr operation. selecting current limit to circuit breaker ratio the ratio of the current limit voltage v limit and circuit breaker voltage v cb can be configured to allow low duty cycle, high crest factor load events like hard drive spin up to operate above the maximum average load current without invoking current limit. avoiding current limit events is a good practice as the load voltage is not glitched un- necessarily by the current limit amplifier and the mosfet power dissipation is kept low. the unlatched cls pin has three input states ( low, open and high). this pin config- ures both hot swap channels simultaneously the preset current limit voltage v limit to approximately 1.5, 2 or 3 of t v cb . however, higher current limit settings will result in higher mosfet power dissipation in the event of a load short. proper choice of the mosfet must accommodate high mosfet power dissipation under the worst case short-circuit. there are three i ftmr(cl) , each corresponds with a v limit selected by the cls input. the typical mosfet soa ( safe operating area) has a constant p 2 t characteristic for single narrow (<10 ms) pulse dissipa- tion. an increase in current (v limit ) for constant mosfet drain/source voltage results in square reduction in allowed stress duration t limit (or square increase in i ftmr(cl) ). the cls pin is internally pulled to 1.23v . if it is driven by a three- state output, the maximum allowable open- circuit leakage is 2a . the driving output must source or sink more than 10 a in the high or low state. if the cls trace crosses noisy digital signal lines, an rc filter close to the cls pin will filter noise pickup ( as shown in figure 1: r 5/c 3). auto-retry vs latchoff the ltc4226 -2 ( automatic retry) version resets the ftmr pin after a 0.5 second delay following a ftmr(h) com- parator timeout if the v cc voltage remains above the 4v undervoltage lockout threshold v cc(uvl) and the on pin remains above its 1.23 v v on threshold. this retry delay can be terminated to force a 50 ms delay restart by cycling v cc below the v cc(uvl) undervoltage threshold or a 10 ms delay restart by cycling the on pin below the v on threshold. the latchoff option ( ltc4226-1) does not reset ftmr(l) comparator automatically. it requires voltage cycling at either the on pin or the v cc pin to reset ftmr pin. resetting faults the circuit breaker fault can be reset by cycling the on pin below and then above the on comparator threshold. there is a turn on delay of 10 ms after the on pin transitions high. alternatively, the v cc pin can be cycled below and then above the undervoltage lockout threshold to reset faults. there is a turn on delay of 50 ms after the v cc pin exits the undervoltage lockout. the ftmr pin reset begins with the ftmr pin pulled down with 100 a to ground. this is followed by a start-up with a 10a fault pin pull-up and a 9a gate pin pull-up.
ltc 4226 15 4226f fault status the fault status pin is active low with a 10 a current source pull-up to a diode below its internal supply volt- age, typically 5 v for any v cc >7 v. when a fault occurs, the fault pin pulls to ground with a 5 ma limit. although the fault pin has the same voltage rating as the supply pin, sinking led current as in figure 9 requires a series resistor to reduce pin power dissipation. the fault pin is also an unlatched input to synchronize the mosfet gate. pulling this pin externally below 0.3v causes the gate to shutoff immediately. this pin can optionally be wire-ored with other ltc4226's fault pins to turn off their gates when one of the ltc4226 has a circuit breaker fault with the ftmr pin asserted at v ftmr(h) . the other ltc4226's ftmr pin is unaffected by the low external fault input. when the ltc4226 with fault is reset ( see section on auto-retry and resetting faults), the wire-ored fault pins return high and the gates revert to their prior states. it is not recommended to connect an led to wire-ored fault pins. daisy chained ports figure 7, illustrates firewire power distribution with ltc4226 hot swap circuits and supply diode-oring. the firewire devices can be power providers or power consumers and can be daisy chained together. in figure 8, a 2-port device allows either port to be powered internally through diode d 1 or to be powered from the op- posite port. the higher voltage source delivers power to the external port devices and the internal firewire controller interface. this permits the host power to be shutdown while the firewire controller remains active with external power provided by the port. the port can relay actively current limited power as long as there are power sources in the chain. more than two ports per device are possible permit- ting power consumption or distribution among multiple ports. the ports allow live plugging and unplugging with port load capacitances as large as 1 mf at 33 v for figure ?8. the output port step up surge current is actively limited. figure 9 shows a 12 v host power source application that can drive a remote load capacitance up to 100 f with a small mosfet like the si2318ds . 2 ma rated leds can be used as fault indicators with resistors to reduce power dissipation at the fault pins. v cc overvoltage detection the ftmr pin can be used to detect a v cc overvoltage condition with a zener diode z2 as shown in figure 6. resistor r5 and zener z3 protect the ftmr pin from excessive voltage while r6 provides a ground path. an overvoltage at v cc beyond 35 v will pull the ftmr pin above 1.23 v through diode d2a and force a fault status. if v cc has a transient suppressor as shown in figure 10, the overvoltage threshold should be set at 35 v which is below the transient suppressor smcj33a minimum breakdown voltage of 36.7v. r5 1k ftmr v cc d2a 1n4148 z3 3v z2 33v 4226 f06 r6 1m figure 6. v cc overvoltage detection a pplica t ions i n f or m a t ion supply transient protection all pins on the ltc4226 are tested for 44 v operation with the exception of ftmr and gate. the gate pins are volt- age clamped either to out or gnd while the ftmr pins are low voltage. if greater than 44 v supply transients are possible, 33 v transient suppressors are highly recom- mended at the v cc pins to clamp the voltage below the 55v absolute maximum voltage rating of the pins. output positive overvoltage isolation transient voltage suppressors are adequate for clamping short overvoltage pulses at the ports, but they may over- heat if forced to sink large currents for extended periods. figure 10 shows how series mosfets can be used to isolate positive port voltages up to the mosfet v bvdss . q3 and q4 are turned off when the overvoltage detection zener z2 pulls both ftmr1 and ftmr2 high through d2a and d2b. the resistors r7 and r8 with mosfets q5 and q6 facilitate restart by pulling up through the body diodes of q1 and q2, respectively.
ltc 4226 16 4226f figure 8. 2-port firewire master or slave application z1 smcj33a ftmr1 gnd c t1 220nf optional 7v to 33v r s1 30m d1 ss3p5 q1 fdms86500dc or si7164dp r s2 30m q2 fdms86500dc or si7164dp c t2 220nf ftmr2 on1 v cc1 sense1 gate1 ltc4226-2 out1 v cc2 sense2 gate2 out2 fault1 cls fault2 on2 phy optional controller v reg c1 10f + r3 150k r4 50k r1 150k r2 50k port 1 1394 socket 1394 plug 4226 f08 port 2 1394 socket 1.5a 1.5a 1394 plug a pplica t ions i n f or m a t ion 4226 f07 node a power provider (master) node b node c power source ltc4226 power consumer power path power consumer 1394 socket 1394 plug 1394 socket 1394 socket 1394 socket 1394 plug 1394 socket 1394 socket 1394 socket 1394 plug 1394 plug node d alternate power provider (slave) power source ltc4226 1394 socket 1394 socket 1394 plug 1394 plug ltc4226 ltc4226 power path figure 7. firewire power distribution example
ltc 4226 17 4226f figure 9. 12v firewire ports with led fault indicators z1 dflt15a ftmr1 gnd c t1 15nf optional 12v r s1 33m d1 ss3p5 q1 si2318cds r s2 33m q2 si2318cds c t2 15nf ftmr2 on1 v cc1 sense1 gate1 ltc4226-2 out1 v cc2 sense2 gate2 out2 fault1 cls fault2 on2 port 1 1394 socket 1394 plug 4226 f09 port 2 1394 socket 1.35a 1.35a 1394 plug r1 4.7k led1 fault indicators r2 4.7k led2 z1 smcj33a ftmr1 gnd c t1 220nf optional 7v to 33v r s1 30m d1 ss3p5 q1 fdms86500dc or si7164dp r s2 30m q2 fdms86500dc or si7164dp c t2 220nf ftmr2 on1 v cc1 sense1 gate1 ltc4226-2 out1 v cc2 sense2 gate2 out2 fault1 cls fault2 on2 q3 fdms2672 or si7172dp q4 fdms2672 or si7172dp q5 bss139 q5 bss139 phy optional controller v reg c1 10f + z3 3v z2 33v r3 150k r4 50k r1 150k r2 50k r6 1m r8 1k d2b mmbd4148ca d2a mmbd4148ca r g1 10 r g2 10 r7 1k r5 1k port 1 1394 socket 1394 plug 4226 f10 port 2 1394 socket 1.5a 1.5a 1394 plug figure 10. 2 firewire ports with positive overvoltage isolation a pplica t ions i n f or m a t ion
ltc 4226 18 4226f figure 11. recommended layout design example as a design example, take the following specifications for figure 8 with a load capacitor c out of 1mf ( not shown on schematic) at the cable end of port 1: the channel is rated for a maximum v cc of 33 v at 1.5a, c out ?= 1 mf and current limit at 1.5 of circuit breaker current. circuit breaker current plus a 15% margin: i cb = 1.5a ? 1.15 = 1.725a, sense resistor: r s = 50mv 1.5a s 1.15 29m start-up in current limit with cls low, v limit = 1.5 ? 1.15 ? v cb and i limit = 1.5 ? 1.15 ? i cb 2.98a calculate the time it takes to charge up c out in current limit: t charge = c out s v cc i limit 11ms during a normal start-up where all of the current charges c out , the average power dissipation in the mosfet is given by: p diss = v cc s i limit 2 = 49.2w if the output is shorted to ground, the average power dissipation in mosfet doubles: p diss = v cc ? i limit = 98.4w the soa ( safe operating area) curve for the fdms86500dc mosfet shows 100 w for 35 ms. during a normal start- up the mosfet dissipates 49.2 w for 11 ms at 33 v with adequate soa margin. setting the current limit fault timeout at about 14 ms gives: c t = t limit s 20a 1.23v = 228nf choose a standard value of 220 nf. the resulting ftmr timeout in current limit is: t limit = 13.5ms the ftmr circuit breaker timeout is: t cb = 135ms the resistor pair r1 and r2 sets the on threshold voltage for both channels. in this case r1 = 150k, r2 = 50k: v cc on threshold = r1 + r2 ( ) s 1.23 r2 = 4.92v layout considerations to achieve accurate current sensing, kelvin connections for the sense resistor are recommended. the pcb layout of kelvin sensing traces should be balanced, symmetrical and minimized to reduce error. in addition, the pcb layout for the sense resistors and the power mosfets should include good thermal management techniques for device power dissipation such as vias and wide metal area. a recommended pcb layout for the sense resistor and power mosfet is illustrated in figure 11. to avoid the need for the additional mosfet gate pin resistor ( r1 in figure 13), the gate trace over ground plane should have minimized trace length and capacitance. a pplica t ions i n f or m a t ion r g2 r s2 4226 f11 r g1 1 r s1 q1 q2 ltc4226
ltc 4226 19 4226f in hot swap applications where load currents can be 5 a, narrow pcb tracks exhibit more resistances than wide tracks and operate at elevated temperatures. the mini- mum trace width for 1 oz copper foil is 0.02 " per amp to make sure the trace stays at a reasonable temperature. using 0.03 " per amp or wider is recommended. note that 1oz copper exhibits a sheet resistance of about 0.5m/ square. the use of vias allow multi-copper planes to be used to improve both electrical conduction and thermal dissipation. thicker top and bottom copper such as 3oz or more can improve electrical conduction and reduce pcb trace dissipation. it is important to minimize noise pickup on pcb traces for on, ftmr, fault , cls and gate. if an r g resistor is used, place the resistor as close to the mosfet gate as possible to limit the parasitic trace capacitance that leads to mosfet self-oscillation. bidirectional current limiting figure 16 shows an application with bidirectional current limiting with a common sense resistor. figure 12 shows an asymmetric bidirectional current limiter for operating voltage between 7 v and 30 v using two separate sense a pplica t ions i n f or m a t ion resistors. separate resistors allow different current limit in each direction to be set. the transient suppressor at the sense pins allow the circuit breaker to trip when either the input or output voltage exceeds the suppressor breakdown voltage. when the out voltage exceeds the suppressor breakdown, gate2 shuts down after ftmr2 time-out and this can prevent suppressor blow out. the timing capacitor at ftmr2 can be selected to keep the suppressor within safe operating area. high current applications figure 13 and figure 14 show 44 a and 89 a continuous current applications for bus power distribution. the bus connection inductance causes a supply dip at the sense resistor when there is a load transient. the worst transient is a short at the output or the sudden connection of an uncharged load capacitor. without capacitors c1 and c2 for channel 1, v cc1 voltage can dip below the ltc4226 undervoltage lockout threshold resulting in a channel 1 uvlo reset. the low esr electrolytic capacitor c1 and ceramic capacitor c2 should be placed very close to the sense resistor v cc1 terminal and the ground plane to minimize inductance. figure 12. 7v to 30v asymmetric bidirectional current-limiter smcj33a ftmr1 gnd 220nf 50m fdms86500dc or si7164dp 220nf ftmr2 on1 sense2 v cc2 gate1 ltc4226-2 out1 fault1 cls fault2 on2 fault1 cls fault2 30m v cc1 sense1 fdms86500dc or si7164dp gate2 out2 out 7v to 30v range 1.48a/0.89a v in 7v to 30v range 4226 f12
ltc 4226 20 4226f a pplica t ions i n f or m a t ion at the occurrence of severe load transient, the gate1 voltage undershoots the voltage needed for current limit regulation. the r g1 and c cg1 network between gate1 and out1 help restore gate1 voltage quickly to the voltage needed for current limit regulation. when a heatsink is a used and gate interconnect has significant capacitance and inductance, optional resistors r1 and r2 can be inserted close to the mosfets gate to prevent parasitic oscillation. the product of r1 and mosfet c iss add delay to the cur- rent limit response. for short pcb gate interconnection, these optional resistors are not needed. tw o hot swap channels with identical sense resistors and mosfets can have their outputs connected together to almost double the current output capability without significant improvement in mosfets soa. output1 in figure 14 can be connected to output2 to give 178a. ftmr1 and ftmr2 should be kept separate as capaci- tors c t1 and c t2 individually monitor the sense voltages across r s1 and r s2 respectively. in the event of a current fault, one channel may time out earlier than the adjacent channel due to mismatch. if fau lt1 and fau lt2 are kept separate, the current in the channel of the first fault is diverted to the adjacent channel with a second fault time out occurring later. now consider the case where fau lt1 and fau lt2 are tied together during a current fault. first fault channel fau lt1 pulls low and this causes an input low at fau lt2 with gate2 pulling low immediately. ftmr2 does not time out due to the common fault connection with gate2 disabled earlier than the case of separate fault connection. the mosfet q1 where the first occurrence of current fault occurs would not be stressed as much as q2 since the fully enhanced q2 determines the parallel channels v cc and out voltage drop. common on pin connections are preferred for parallel channel applications. figure 13. dual continuous 44a typical output z1 sm6s15ahe3/2d ftmr1 gnd c t1 10nf 12v r s1 1m q1 irf2804s-7ppbf r s2 1m q2 irf2804s-7ppbf c t2 10nf ftmr2 on1 v cc1 sense1 gate1 ltc4226-2 out1 v cc2 sense2 gate2 out2 fault1 cls fault2 on2 on1 fault1 fault2 on2 output1 12v, 44a output2 12v, 44a 4226 f13 r2 10k r1 10k c1 1000f 25v + r g1 10 c2 22f 10 25v x5r c3 1000f 25v + c4 22f 10 25v x5r c g1 10nf r g2 10 c g2 10nf
ltc 4226 21 4226f a pplica t ions i n f or m a t ion figure 14. dual continuous 89a typical output z1 sm8s15ahe3/2d ftmr1 gnd c t1 1nf +12v r s1 0.5m q1 irf1324s-7ppbf r s2 0.5m q2 irf1324s-7ppbf *optional connection option to share mosfet soa c t2 1nf ftmr2 on1 v cc1 sense1 gate1 ltc4226-2 out1 v cc2 sense2 gate2 out2 fault1 cls fault2 on2 on1 fault1 fault2 on2 output1 12v, 89a output2 12v, 89a 4226 f14 r4 10k r3 10k c1 1000f 2 25v + r g1 10 c2 22f 20 25v x5r c3 1000f 2 25v + c4 22f 20 25v x5r c g1 10nf r g2 10 r2* 10 r1* 10 c g2 10nf one drawback of the separate ftmr scheme for parallel channels is that one timer may ramp up in current limit mode before the other channel, resulting in shorter circuit breaker timer duration and/or a reduction in the combined circuit breaker current threshold due to r ds( on) mismatch. these issues are solved by using two cross-coupled pnp clamps connected between the ftmr pins as shown in fig- ure 15. the fault pins are shorted together and connected to an external open drain pull-down which is controlled by a gate synchronization signal. the pnps prevent a current limited channels ftmr from ramping up too fast while the other channel is still in circuit breaker mode. if only one of the channels is in current limit mode, the clamp from the other channel will slow down the current limited channels ftmr ramp rate as shown in figure 15 s accom- panying waveforms. this scheme assumes common v cc and on pins, and both channels should be on the same chip. channel to channel matching is 6% for v cb , 6% for v limit , and gate high skew delay timing for both on and v cc are 10%. the gate pins must be synchronized by asserting the f ault inputs low to mask out t on(uvl) skew. asserting the fault pins low for at least 100 ms at power-up will ensure that the mosfets turn on together. c t2 10nf ltc4226 fault2 fault ftmr2 delayed c t1 10nf fault1 ftmr1 q3 2n3906 q4 2n3906 4226 f15 1ms/div ftmr 0.5v/div fault 5v/div i out 5a/div ftmr1 fault ftmr2 total output current on off figure 15. pnp connected ftmr for 2 parallel channels
ltc 4226 22 4226f p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.65 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-4) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.65 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 ? 0.05 (ud16 var a) qfn 1207 rev a 0.25 0.05 0.50 bsc package outline ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1700 rev a) exposed pad variation aa
ltc 4226 23 4226f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms16) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?)
ltc 4226 24 4226f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 1012 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc1421 dual channel hot swap controller operates from 3v to 12v, supports C12v ltc1422 single channel hot swap controller operates from 2.7v to 12v ltc1645 dual channel hot swap controller operates from 3v to 12v, power sequencing, ltc1647 dual channel hot swap controller operates from 2.7v to 16.5v ltc4210 single channel hot swap controller operates from 2.7v to 16.5v, active current limiting ltc4211 single channel hot swap controller operates from 2.5v to 16.5v, multifunction current control ltc4215 single hot swap controller with adc and i 2 c interface operates from 2.9v to 15v, monitors voltage and current with 8-bit adc ltc4216 single channel hot swap controller operates from 0v to 6v ltc4218 single channel hot swap controller operates from 2.9v to 26.5v, adjustable, 5% accurate (15mv) current limit LTC4222 dual hot swap controller with adc and i 2 c interface operates from 2.9v to 29v, digitally monitors voltage and current with 10-bit adc ltc4224 dual channel hot swap controller operates from 1v to 6v ltc4227 dual ideal diode and single hot swap controller operates from 2.9v to 18v ltc4228 dual ideal diode and hot swap controller operates from 2.9v to 18v ltc4230 triple channel hot swap controller operates from 1.7v to 16v, multifunction current control ltc4280 single hot swap controller with adc and i 2 c interface operates from 2.9v to 15v, monitors voltage and current with 8-bit adc ltc4352 ideal diode controller with monitoring operates from 0v to 18v, uv, ov ltc4364 surge stopper/hot swap controller with ideal diode operates from 4v to 80v, C40v reverse input figure 16. bidirectional current-limiter smcj33a ftmr1 gnd 220nf 30m si7164dp 220nf ftmr2 on1 v cc1 v cc2 sense1 gate1 ltc4226-2 out1 sense2 fault1 cls fault2 on2 fault1 cls fault2 si7164dp gate2 out2 out 7v to 30v 1.48a v in 7v to 30v 4226 f16

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